hpnsaPciStatus
HPNSAPCI-MIB ·
.1.3.6.1.4.1.11.2.23.10.4.1.1.10
Object
column
mandatory
Integer32
Status information for PCI bus related events.
Bit Description
--- ------------
0-6 Reserved
7 Fast Back-to-Back Capable
8 Data Parity Detected
9-10 DEVSEL timing; 00=fast, 01=medium, 10=slow
11 Signal Target Abort
12 Received Target Abort
13 Received Master Abort
14 Signaled System Error
15 Detected Parity Error
Context
- MIB
- HPNSAPCI-MIB
- OID
.1.3.6.1.4.1.11.2.23.10.4.1.1.10- Type
- column
- Access
- readonly
- Status
- mandatory
- Parent
- hpnsaPciEntry
- Table
- hpnsaPciTable
- Siblings
- 19
Syntax
Integer32
- Source
- COPS-PR-SPPIInteger32
- Base type
Integer32
Values & Constraints
Type Constraints
range: -2147483648..2147483647
Related Objects
Sibling Objects
| Object | Type | Syntax | OID |
|---|---|---|---|
| hpnsaPciBusIndex mandatory The PCI Bus number that this entry describes. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.1 |
| hpnsaPciCacheLineSize mandatory Specifies the system cache line size in units of 32-bit words. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.11 |
| hpnsaPciLatencyTimer mandatory Specifies, in units of PCI bus clocks, the value of the
Latency Timer for this PCI bus master. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.12 |
| hpnsaPciBist mandatory This optional register is used for control and status
of Built-in Self Test. Devices that don't support BIST
must always return a value of 0.
Bit Description
--… | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.13 |
| hpnsaPciInterruptLine mandatory Communicates interrupt line routing information. The value
in this register tells which input of the system interrupt
contoller(s) the device's interrupt pin is connected to. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.14 |
| hpnsaPciInterruptPin mandatory Tells which interrupt pin the device uses. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.15 |
| hpnsaPciMaxLat mandatory Specifies how often the device needs to gain access to
the PCI bus. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.16 |
| hpnsaPciMinGnt mandatory Specifies how long a burst period the device needs assuming
a clock rate of 33MHz. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.17 |
| hpnsaPciBaseAddrRegs mandatory Base address mapping registers for memory and IO. Refer
to the PCI specification for the format. | column | OctetString | .1.3.6.1.4.1.11.2.23.10.4.1.1.18 |
| hpnsaPciExpRomBaseAddr mandatory 4-byte register is defined to handle the base address
and size information for an expansion ROM.
Bit Description
--- ------------
31-11 Expansion ROM Bas… | column | OctetString | .1.3.6.1.4.1.11.2.23.10.4.1.1.19 |
| hpnsaPciDeviceIndex mandatory The PCI device or slot number that this entry describes. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.2 |
| hpnsaPciDeviceSpecific mandatory Device specific configuration space. | column | OctetString | .1.3.6.1.4.1.11.2.23.10.4.1.1.20 |
| hpnsaPciSlotNumber mandatory The physical PCI slot number | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.21 |
| hpnsaPciFunctionIndex mandatory The PCI function that this entry describes. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.3 |
| hpnsaPciDeviceId mandatory Identifies the particular device. This identier is allocated
by the vendor.
Device ID Description
--------- ------------
XXXX Blah! Blah! | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.5 |
| hpnsaPciRevisionId mandatory Specifies a device specific revision identifier. | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.6 |
| hpnsaPciHeaderType mandatory Idendifies the layout of bytes 10h-3Fh in configuration
space and whether or not the device contains multiple
functions.
Bit 7: 1=multi-function device, 0=single… | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.7 |
| hpnsaPciClassCode mandatory Identifies the generic function of the device.
Base Sub- Prog
Class Class If. Meaning
----- ----- ----- -------
00h Device buil… | column | OctetString | .1.3.6.1.4.1.11.2.23.10.4.1.1.8 |
| hpnsaPciCommand mandatory Provides course control over a device's ability to generate
and respond to PCI cylces.
Bit Description
--- ------------
0 IO Space
1 Memory Spac… | column | Integer32 | .1.3.6.1.4.1.11.2.23.10.4.1.1.9 |