hpnsaPciExpRomBaseAddr

HPNSAPCI-MIB · .1.3.6.1.4.1.11.2.23.10.4.1.1.19
MIB view Table view

Object

column mandatory OctetString 
4-byte register is defined to handle the base address
and size information for an expansion ROM.
              
Bit     Description
---     ------------
31-11    Expansion ROM Base Address (upper 21 bits)
10-1     Reserved
 0      0 = address decoding is disabled and no access
	     to this space are allowed.
	 1 = address decoding enabled.

Context

MIB
HPNSAPCI-MIB
OID
.1.3.6.1.4.1.11.2.23.10.4.1.1.19
Type
column
Access
readonly
Status
mandatory
Parent
hpnsaPciEntry
Table
hpnsaPciTable
Siblings
19

Syntax

OctetString

Values & Constraints

Object Constraints
range: 4-4

Related Objects

Sibling Objects
ObjectTypeSyntaxOID
hpnsaPciBusIndex mandatory
The PCI Bus number that this entry describes.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.1
hpnsaPciStatus mandatory
Status information for PCI bus related events. Bit Description --- ------------ 0-6 Reserved 7 Fast Back-to-Back Capable 8 Data Parity Detec…
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.10
hpnsaPciCacheLineSize mandatory
Specifies the system cache line size in units of 32-bit words.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.11
hpnsaPciLatencyTimer mandatory
Specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.12
hpnsaPciBist mandatory
This optional register is used for control and status of Built-in Self Test. Devices that don't support BIST must always return a value of 0. Bit Description --…
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.13
hpnsaPciInterruptLine mandatory
Communicates interrupt line routing information. The value in this register tells which input of the system interrupt contoller(s) the device's interrupt pin is connected to.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.14
hpnsaPciInterruptPin mandatory
Tells which interrupt pin the device uses.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.15
hpnsaPciMaxLat mandatory
Specifies how often the device needs to gain access to the PCI bus.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.16
hpnsaPciMinGnt mandatory
Specifies how long a burst period the device needs assuming a clock rate of 33MHz.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.17
hpnsaPciBaseAddrRegs mandatory
Base address mapping registers for memory and IO. Refer to the PCI specification for the format.
columnOctetString.1.3.6.1.4.1.11.2.23.10.4.1.1.18
hpnsaPciDeviceIndex mandatory
The PCI device or slot number that this entry describes.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.2
hpnsaPciDeviceSpecific mandatory
Device specific configuration space.
columnOctetString.1.3.6.1.4.1.11.2.23.10.4.1.1.20
hpnsaPciSlotNumber mandatory
The physical PCI slot number
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.21
hpnsaPciFunctionIndex mandatory
The PCI function that this entry describes.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.3
hpnsaPciDeviceId mandatory
Identifies the particular device. This identier is allocated by the vendor. Device ID Description --------- ------------ XXXX Blah! Blah!
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.5
hpnsaPciRevisionId mandatory
Specifies a device specific revision identifier.
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.6
hpnsaPciHeaderType mandatory
Idendifies the layout of bytes 10h-3Fh in configuration space and whether or not the device contains multiple functions. Bit 7: 1=multi-function device, 0=single…
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.7
hpnsaPciClassCode mandatory
Identifies the generic function of the device. Base Sub- Prog Class Class If. Meaning ----- ----- ----- ------- 00h Device buil…
columnOctetString.1.3.6.1.4.1.11.2.23.10.4.1.1.8
hpnsaPciCommand mandatory
Provides course control over a device's ability to generate and respond to PCI cylces. Bit Description --- ------------ 0 IO Space 1 Memory Spac…
columnInteger32.1.3.6.1.4.1.11.2.23.10.4.1.1.9