cmgDsuInvertTxC

G700-MG-MIB · .1.3.6.1.4.1.6889.2.9.1.1.11.2.1.1.8
MIB view Table view

Object

column obsolete r/w Enumeration 
Specifies whether the clock supplied by the DSU/CSU on the TXC
interchange circuit DB (CCITT 114) is phase inverted with respect
to the Transmitted Data interchange ciucuit BA (CCITT 103).  This
option is useful when long cable lengths between the DSU/CSU and
the DTE are causing data errors.

Context

MIB
G700-MG-MIB
OID
.1.3.6.1.4.1.6889.2.9.1.1.11.2.1.1.8
Type
column
Access
readwrite
Status
obsolete
Parent
cmgDsuConfigEntry

Syntax

Enumeration

Values & Constraints

Enumerated Values
1enabled
2disabled