zhnPwClkAcquisitionLevel

The PLL clock acquisition level from 0 - 15. Level 8 or higher is required 
for reliable operation. During the clock acquisition process, the Phase Lock 
Loop moves through 16 adjustment levels. Level 0 is the starting phase, with 
very coarse adjustments. Level 15 is the final phase, with very fine adjustment. 
Once level 8 has been reached, the acquired clock is highly accurate.
This object is also referred to as the PWE Adaptive Clock Counter.

MIB

ZHNPWMIB

OID

.1.3.6.1.4.1.5504.2.5.31.1.1.1.21

Type

column

Access

readonly

Status

current

Parent

zhnPwEntry