cpqDaAccelWriteErrs

Cache Module Board Write Errors.
              
This shows the total number of write memory parity errors that
were detected while writing to the Cache Module board.
              
Write parity errors occur when the system detects that
information has not been transferred to the Cache
Module board correctly.  A parity bit is included for
each byte of information stored in memory.  When the
microprocessor reads or writes data, the system counts the
value of the bits in each byte.  If the total does not match
the system`s expectations, a parity error has occurred.

MIB

CPQIDA-MIB

OID

.1.3.6.1.4.1.232.3.2.2.2.1.8

Type

column

Access

readonly

Status

mandatory

Parent

cpqDaAccelEntry