dsx3LineBERTPattern

CISCO-MGX82XX-DSX3-MIB · .1.3.6.1.4.1.351.110.4.4.1.1.1.1.11

Object

column r/w Enumeration
This object defines the test bit pattern to be
used for BERT.
              
The possible values are :
              
  Repetitive Patterns
              
allZero(1): All Zeroes(Continuous spaces).  This is 
        repeating pattern of zeros(...000...). 
        The use of this pattern is to test and verify 
        that the ones density policing mechanism is 
        functioning properly.  This pattern must be 
        used in circuits optioned for B8ZS.
              
allOnes(2): All Ones(Continuous Marks).  This is repeating
        pattern of ones(...1111...).  This provides 
        testing of maximum power level requirements.
        The all one pattern test causes the repeater 
        to consume the maximum amount of power. 
        If there is insufficient DC span power then the
        repeater may begin to fail.
        Typically this pattern is used for a simple
        continuity check.  It may also be used to detect
        the presence of unwanted loop in the network.
              
alternateOneZero(3): Alternate one/zero pattern(..1010..).  This
        pattern produces a 50% ones density.  It is
        used to stress the repeater's DC power
        consumption.
              
doubleOneZero(4): Double alternate one/zero(..1100..).
              
 userOneWord(5),
 userTwoWords(6),
 userThreeWords(7),
 userFourWords(8),
 pattern2p15minus1(9) :
   This is the 2^15-1(32767 bit length)
   pattern as specified in ITU O.151.
   It has the maximum of 15(inverted) sequential zeros.
   This sequence is primarily intended for
   error and jitter measurements at bit
   rates of 1544, 2048, 6312, 8448,
   32064 and 44736 kbit/s.
              
 pattern2p20minus1(10): 
   This is the 2^20-1(1048575 bits in length)
   pattern specified in ITU O.153.It has
   the maximum of 19(non-inverted) sequential
   zeros.  This pattern is primarily intended 
   for error measurements at bit rates up to 
   73kbit/s.  This pattern stresses the 
   equalization and timing recovery circuitry 
   of line repeaters.
              
  pattern2p23minus1(11):
     This is the 2^23-1(1048575 bits in length) pattern.

Context

MIB
CISCO-MGX82XX-DSX3-MIB
OID
.1.3.6.1.4.1.351.110.4.4.1.1.1.1.11
Type
column
Access
readwrite
Status
current
Parent
cwDsx3ConfigEntry
Table
cwDsx3ConfigTable
Siblings
31

Syntax

Enumeration

Values & Constraints

Enumerated Values
1allZero
2allOnes
3alternateOneZero
4doubleOneZero
5userOneWord
6userTwoWords
7userThreeWords
8userFourWords
9pattern2p15minus1
10pattern2p20minus1
11pattern2p23minus1

Related Objects

Sibling Objects