dsx1SfpClkConfigClkControlSignal

ASAM-SFP-MIB · .1.3.6.1.4.1.637.61.1.56.10.1.7
MIB view Table view

Object

column mandatory r/w Enumeration 
SEL_LOC_OR_SRC. Control signal to select the VTCXO control signal
(PWM) between DPLL output and a ~4MHZ square wave signal
generated dividing the same system clock.
		0  Square wave generated from system clock.
		1  Control signal from PLL(Phase locked loop).
               
ALCATEL NOTE: 
 ACCESS: RW
 USAGE: NA
 PERSIST: YES 
 INSRVMOD: NA
 RANGE: 0,1
 DEFVALUE: 0
 UNITS: NA 
 SPARSE: NO
 DESCR: NA

Context

MIB
ASAM-SFP-MIB
OID
.1.3.6.1.4.1.637.61.1.56.10.1.7
Type
column
Access
readwrite
Status
mandatory
Parent
dsx1ClockConfigEntry

Syntax

Enumeration

Values & Constraints

Enumerated Values
0squarewave
1pll