hdlcRxClockPolarity
ACE202-MIB ·
.1.3.6.1.4.1.164.3.1.6.5.1.1.11
Object
column
r/w
Enumeration
normal - The received data is sampled at the middle of bit time inverse - The received data is sampled at the end of the bit time (high data rate/long cable).
Context
- MIB
- ACE202-MIB
- OID
.1.3.6.1.4.1.164.3.1.6.5.1.1.11- Type
- column
- Access
- readwrite
- Status
- current
- Parent
- hdlcEntry
Syntax
Enumeration
Values & Constraints
Object Constraints
range: 4-4