pktSwchFrTxCeilingS
RAD-MIB ·
.1.3.6.1.4.1.164.8.8.2.1.8
Object
column
r/w
Integer32
The maximum allowable transmit pool for this port.
Context
- MIB
- RAD-MIB
- OID
.1.3.6.1.4.1.164.8.8.2.1.8- Type
- column
- Access
- readwrite
- Status
- current
- Parent
- pktSwchFrSEntry
- Table
- pktSwchFrSTable
- Siblings
- 14
Syntax
Integer32
Values & Constraints
No enumerated values or constraints recorded.
Related Objects
Sibling Objects
| Object | Type | Syntax | OID |
|---|---|---|---|
| pktSwchFrIfIndexS This is the ifIndex of the frame relay port. | column | SNMPv2-SMIInteger32 | .1.3.6.1.4.1.164.8.8.2.1.1 |
| pktSwchFrNrzModeS The data encoding format. | column | Enumeration | .1.3.6.1.4.1.164.8.8.2.1.10 |
| pktSwchFrDlciHeaderModeS Dlci Header length for this FR port. Option 4 means that there
will be no management Dlci in the range of 1024 to 8388607.
The management Dlci will be in the range of 0-15 or 991-… | column | Enumeration | .1.3.6.1.4.1.164.8.8.2.1.11 |
| pktSwchFrDcdLinkFailureS Link Failure Detection by DCD.
If Link Failure detection by DCD is on - (3), when the DCD is
down, the FR SW will detect it and change the FR link status
from UP to DOWN. A trap o… | column | Enumeration | .1.3.6.1.4.1.164.8.8.2.1.12 |
| pktSwchFrTxIdlesS This parameter shows whether the PS will Transmit Idles between
frames and control the RTS pin.
Default: no(2). | column | Enumeration | .1.3.6.1.4.1.164.8.8.2.1.13 |
| pktSwchFrOperationModeS When H/W Control is configured, the SCC H/W will detect the change in the
DCD or CTS signals and Start or Stop transmission automatically.
When S/W Control is configured the S/W w… | column | Enumeration | .1.3.6.1.4.1.164.8.8.2.1.14 |
| pktSwchFrPhysInterfOptionsS This is the physical interface.
Note that the DDS physical interface H/W does not exist in the FPS-8.
It is relevant for other PS devices only.
For FPS-8 only the default (noOptio… | column | Enumeration | .1.3.6.1.4.1.164.8.8.2.1.15 |
| pktSwchFrMaintProtS This defines what maintenance protocol is running over this port.
0 - No maintenance protocol.
1 - ANSI PVC maintenance protocol running on DLCI number 0.
2 - LMI maintenance prot… | column | Integer32 | .1.3.6.1.4.1.164.8.8.2.1.2 |
| pktSwchFrMaintModeS This defines the mode of maintenance protocol running over this port. | column | Enumeration | .1.3.6.1.4.1.164.8.8.2.1.3 |
| pktSwchFrRxPoolRedLineS When the number of empty receive buffers at the port reaches this
figure (of frames),the port receiver is congested. This field
value should be less than the Rx pool OK field. | column | Integer32 | .1.3.6.1.4.1.164.8.8.2.1.4 |
| pktSwchFrRxPoolOkS Clear the receive congestion condition when the number of empty
receive buffers at the port reaches this figure. This value
(of frames) should be greater than the Rx pool red lin… | column | Integer32 | .1.3.6.1.4.1.164.8.8.2.1.5 |
| pktSwchFrTxPoolRedLineS When the number of frames awaiting transmission reaches this figure,
the port transmitter is congested. This field value should be
greater than the Tx pool OK field. | column | Integer32 | .1.3.6.1.4.1.164.8.8.2.1.6 |
| pktSwchFrTxPoolOkS Clear the transmit congestion condition when the number of frames
awaiting transmission at the port reaches this figure. This value
(of frames) should be less than the Tx pool re… | column | Integer32 | .1.3.6.1.4.1.164.8.8.2.1.7 |
| pktSwchFrInternalClockS The baud rate of the internal clock. | column | Enumeration | .1.3.6.1.4.1.164.8.8.2.1.9 |