cimrMsuDistEntry
CISCO-ITP-MSU-RATES-MIB ·
.1.3.6.1.4.1.9.9.529.1.2.3.1
Object
row
Each entry represents a processor and is updated at end of interval specified by the cimrMsuRateSampleInterval object.
Context
- MIB
- CISCO-ITP-MSU-RATES-MIB
- OID
.1.3.6.1.4.1.9.9.529.1.2.3.1- Type
- row
- Status
- current
- Parent
- cimrMsuDistTable
- Table
- cimrMsuDistTable
- Children
- 10
Syntax
No syntax metadata recorded.
Values & Constraints
No enumerated values or constraints recorded.
Related Objects
Child Objects
| Object | Type | Syntax | OID |
|---|---|---|---|
| cimrMsuDist000to009Seconds The total number of seconds during which the MSU rate
for this processor was from 0 to 9 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.1 |
| cimrMsuDist090orAbove The total number of seconds during which the MSU rate
for this processor was above 90 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.10 |
| cimrMsuDist010to019Seconds The total number of seconds during which the MSU rate
for this processor was from 10 to 19 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.2 |
| cimrMsuDist020to029Seconds The total number of seconds during which the MSU rate
for this processor was from 20 to 29 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.3 |
| cimrMsuDist030to039Seconds The total number of seconds during which the MSU rate
for this processor was from 30 to 39 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.4 |
| cimrMsuDist040to049Seconds The total number of seconds during which the MSU rate
for this processor was from 40 to 49 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.5 |
| cimrMsuDist050to059Seconds The total number of seconds during which the MSU rate
for this processor was from 50 to 59 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.6 |
| cimrMsuDist060to069Seconds The total number of seconds during which the MSU rate
for this processor was from 60 to 69 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.7 |
| cimrMsuDist070to079Seconds The total number of seconds during which the MSU rate
for this processor was from 70 to 79 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.8 |
| cimrMsuDist080to089Seconds The total number of seconds during which the MSU rate
for this processor was from 80 to 89 percent of the
current overloaded-threshold value. | column | seconds CirbhMsuCurrentCount | .1.3.6.1.4.1.9.9.529.1.2.3.1.9 |
Indexes
| Object | Type | Syntax | OID |
|---|---|---|---|
| cimrMsuProcIndex An index that uniquely represents a processor. This
index is assigned arbitrarily by the engine and is
not saved over reboots. | column | Unsigned32 | .1.3.6.1.4.1.9.9.529.1.2.1.1.1 |
| cimrMsuTrafficDirection The direction of traffic on a processor. | column | CirbhMsuTrafficDirection | .1.3.6.1.4.1.9.9.529.1.2.2.1.1 |