hpnsaPciExpRomBaseAddr

4-byte register is defined to handle the base address
and size information for an expansion ROM.
              
Bit     Description
---     ------------
31-11    Expansion ROM Base Address (upper 21 bits)
10-1     Reserved
 0      0 = address decoding is disabled and no access
	     to this space are allowed.
	 1 = address decoding enabled.

MIB

HPNSAPCI-MIB

OID

.1.3.6.1.4.1.11.2.23.10.4.1.1.19

Type

column

Access

readonly

Status

mandatory

Parent

hpnsaPciEntry