serialIfClockEdge

The value of IfClockEdge influences the (internal) active
clock edge(s) for generating/sampling data on the serial line. 
 This value should be left on DEFAULT under normal
 circumstances. Nevertheless, in some rare cases it is possible
 the connection does not work properly. This behaviour may be
 produced by timing inconsistencies over the serial line in
 conjunction with some disadvantageous clock/data processing
 at the DTE/DCE devices and is very device couple specific. The
 several settings allow shifting data generation/sampling by
 half a cycle of the incoming serial clock. The variation of
 this setting can help to make a not working connection
 working. A typical sign for an erroneous situation in this
 sense is the reception of massive corrupted frames at one or
 both communication end points.
 default(1)		the clock edges for generating/sampling
 			are the default ones
 rxc-inverted(2)	the receiver's data sampling is shifted
 			by half a cycle of incoming serial
 			clock (currently only supported by
 			X8500)
 txc-inverted(3)	the transmitter's data generation is
 			shifted by half a cycle of incoming
 			serial clock
 rxc-txc-inverted(4)	both the receiver's data sampling and
 			the transmitter's data generation is
 			shifted by half a cycle of incoming
 			serial clock (currently only supported
 			by X8500)

MIB

BIANCA-BRICK-SERIAL-MIB

OID

.1.3.6.1.4.1.272.4.25.1.1.6

Type

column

Access

readwrite

Status

mandatory

Parent

serialIfEntry