issPortCpuControlledLearning

Enables or disables the CPU controlled learning on a port. 
The default behavior is hardware learning. By enabling this object 
software learning on that particular port is enabled.
              
When CPU controlled learning is enabled, for the first time, packet 
will be copied to CPU and source MAC address learning will not happen 
in the hardware. When packet is received at PNAC - if the source MAC 
address is authorized, the packet will be allowed to go through further 
processing. Else, the packet will be dropped.  When packets from 
authorized MAC address are received at VLAN, MAC learning will happen 
at VLAN and the same entry will be programmed in the hardware. Once the 
MAC address is learnt, further forwarding will happen at driver itself.    
              
The Mac address entries which are added through software learning are
checked in periodical intervals for the HIT entry. If there is no
traffic for that entry, the HIT flag won't be set. The entry will be 
removed from the hardware if the hit flag is not set.
Note: When software learning is enabled, rate limiting to the port
needs to be configured

MIB

ARICENT-ISS-MIB

OID

.1.3.6.1.4.1.2076.81.2.2.1.11

Type

column

Access

readwrite

Status

current

Parent

issPortCtrlEntry