genEquipInterfacesPWCardExportClkSysRef

MWRM-NETWORK-MIB · .1.3.6.1.4.1.2281.10.9.7.1.1.2
MIB view Table view

Object

column r/w Enumeration 
Which card clock to provide as source towards system reference clock;
FrontPanel takes the clock inserted into the front panel interface;
ClockRecovery takes the clock recovered from the PW service mapped to the TDM port defined in  ExportClkSysRefCrPort.

Context

MIB
MWRM-NETWORK-MIB
OID
.1.3.6.1.4.1.2281.10.9.7.1.1.2
Type
column
Access
readwrite
Status
current
Parent
genEquipInterfacesPWCardEntry
Table
genEquipInterfacesPWCardTable
Siblings
11

Syntax

Enumeration

Values & Constraints

Enumerated Values
0none
1frontPanel
2clockRecovery

Related Objects

Sibling Objects
ObjectTypeSyntaxOID
genEquipInterfacesPWCardSlotNumber
Slot number where the relevant PW card is inserted.
columnInteger32.1.3.6.1.4.1.2281.10.9.7.1.1.1
genEquipInterfacesPWCardClkRecoveryMode
Clock recovery mode for the card.
columnEnumeration.1.3.6.1.4.1.2281.10.9.7.1.1.10
genEquipInterfacesPWCardDifferentialClkFrequency
Frequency for differential clock (none for adaptive).
columnEnumeration.1.3.6.1.4.1.2281.10.9.7.1.1.11
genEquipInterfacesPWCardDifferentialClkSource
Reference clock source for differential clock recovery (none for adaptive).
columnEnumeration.1.3.6.1.4.1.2281.10.9.7.1.1.12
genEquipInterfacesPWCardExportClkFrontPannel
Which clock to export to the front panel clock; SysRefClk exports the system reference clock; ClockRecovery exports the clock recovered from the PW service mapped to the TDM port …
columnEnumeration.1.3.6.1.4.1.2281.10.9.7.1.1.3
genEquipInterfacesPWCardExportClkSysRefCrPort
TDM port serving as clock recovery reference if ExportClkSysRef is set to ClockRecovery.
columnInteger32.1.3.6.1.4.1.2281.10.9.7.1.1.4
genEquipInterfacesPWCardExportClkFrontPanelCrPort
TDM port serving as clock recovery reference if ExportClkFrontPannel is set to ClockRecovery.
columnInteger32.1.3.6.1.4.1.2281.10.9.7.1.1.5
genEquipInterfacesPWCardFrontPanelClockSignalInput
Configure the type of input clock signal of the front panel port. Sync is 2.048MHz/1.544MHz (differential sine/square 3.3V); e1t1 is a G.823/G.824 signal.
columnEnumeration.1.3.6.1.4.1.2281.10.9.7.1.1.6
genEquipInterfacesPWCardFrontPanelClockSignalOutp
Configure the type of output clock signal of the front panel port. Sync is 2.048MHz/1.544MHz (differential sine/square 3.3V); e1t1 is a G.823/G.824 signal.
columnEnumeration.1.3.6.1.4.1.2281.10.9.7.1.1.7
genEquipInterfacesPWCardIpAddrUdpIpTraffic
IP Address for UDP/IP encapsulated PWs.
columnSNMPv2-SMIIpAddress.1.3.6.1.4.1.2281.10.9.7.1.1.8
genEquipInterfacesPWCardIpSubnetUdpIpTraffic
IP Subnet for UDP/IP encapsulated PWs.
columnSNMPv2-SMIIpAddress.1.3.6.1.4.1.2281.10.9.7.1.1.9