VDSL2-LINE-TC-MIB MIB – Observium MIB Browser

VDSL2-LINE-TC-MIB

        This MIB Module provides Textual Conventions to be
used by the VDSL2-LINE-MIB module for the purpose of
managing VDSL2, ADSL, ADSL2, and ADSL2+ lines.
        
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This version of this MIB module is part of RFC 5650;
see the RFC itself for full legal notices.

Last revised: 30 Sep 2009, 00:00 UTC
Identity: vdsl2TCMIB
Base OID: 1.3.6.1.2.1.10.251.3

Imported Objects

SNMPv2-SMI	MODULE-IDENTITY (no object page) transmission
SNMPv2-TC	TEXTUAL-CONVENTION (no object page)

Net-SNMP examples using the rfc MIB directory Show commands

These commands use the standard Observium installation path and load the selected MIB variant before the RFC and Net-SNMP directories.

Translate the module identity

/usr/bin/snmptranslate -Pud -Ir -On -m 'VDSL2-LINE-TC-MIB' -M '/opt/observium/mibs/rfc:/opt/observium/mibs/net-snmp' 'VDSL2-LINE-TC-MIB::vdsl2TCMIB'

Walk the MIB subtree

/usr/bin/snmpbulkwalk -v2c -c '<community>' -Pud -Ir -OQUs -m 'VDSL2-LINE-TC-MIB' -M '/opt/observium/mibs/rfc:/opt/observium/mibs/net-snmp' 'udp:<hostname>:161' 'VDSL2-LINE-TC-MIB::vdsl2TCMIB'

How SNMP, Net-SNMP, MIB paths, and variants work

Objects (1)

vdsl2TCMIB		`.1.3.6.1.2.1.10.251.3`

Type Definitions (46)

Xdsl2Band	Enumeration	`upstream(1)` `downstream(2)` `us0(3)` `ds1(4)` `us1(5)` `ds2(6)` `us2(7)` `ds3(8)` `us3(9)` `ds4(10)` `us4(11)`
Xdsl2BandUs	Enumeration	`us1(5)` `us2(7)` `us3(9)` `us4(11)`
Xdsl2BitsAlloc	OctetString	`range: 0..256`
Xdsl2BpscResult	Enumeration	`none(1)` `success(2)` `inProgress(3)` `unsupported(4)` `failed(5)` `noResources(6)`
Xdsl2CarMask	OctetString	`range: 0..128`
Xdsl2ChAtmStatus	Bits	`noDefect(0)` `noCellDelineation(1)` `lossOfCellDelineation(2)`
Xdsl2ChInitPolicy	Enumeration	`policy0(1)` `policy1(2)`
Xdsl2ChInpReport	Enumeration	`inpComputedUsingFormula(1)` `inpEstimatedByXtur(2)`
Xdsl2ChPtmStatus	Bits	`noDefect(0)` `outOfSync(1)`
Xdsl2ConfPmsForce	Enumeration	`l3toL0(0)` `l0toL2(2)` `l0orL2toL3(3)`
Xdsl2Direction	Enumeration	`upstream(1)` `downstream(2)`
Xdsl2InitResult	Enumeration	`noFail(0)` `configError(1)` `configNotFeasible(2)` `commFail(3)` `noPeerAtu(4)` `otherCause(5)`
Xdsl2LastTransmittedState	Enumeration	`atucG9941(0)` `atucQuiet1(1)` `atucComb1(2)` `atucQuiet2(3)` `atucComb2(4)` `atucIcomb1(5)` `atucLineprob(6)` `atucQuiet3(7)` `atucComb3(8)` `atucIComb2(9)` `atucMsgfmt(10)` `atucMsgpcb(11)` `atucQuiet4(12)` `atucReverb1(13)` `atucTref1(14)` `atucReverb2(15)` `atucEct(16)` `atucReverb3(17)` `atucTref2(18)` `atucReverb4(19)` `atucSegue1(20)` `atucMsg1(21)` `atucReverb5(22)` `atucSegue2(23)` `atucMedley(24)` `atucExchmarker(25)` `atucMsg2(26)` `atucReverb6(27)` `atucSegue3(28)` `atucParams(29)` `atucReverb7(30)` `atucSegue4(31)` `atucShowtime(32)` `aturG9941(100)` `aturQuiet1(101)` `aturComb1(102)` `aturQuiet2(103)` `aturComb2(104)` `aturIcomb1(105)` `aturLineprob(106)` `aturQuiet3(107)` `aturComb3(108)` `aturIcomb2(109)` `aturMsgfmt(110)` `aturMsgpcb(111)` `aturReverb1(112)` `aturQuiet4(113)` `aturReverb2(114)` `aturQuiet5(115)` `aturReverb3(116)` `aturEct(117)` `aturReverb4(118)` `aturSegue1(119)` `aturReverb5(120)` `aturSegue2(121)` `aturMsg1(122)` `aturMedley(123)` `aturExchmarker(124)` `aturMsg2(125)` `aturReverb6(126)` `aturSegue3(127)` `aturParams(128)` `aturReverb7(129)` `aturSegue4(130)` `aturShowtime(131)` `vtucG9941(200)` `vtucQuiet1(201)` `vtucChDiscov1(202)` `vtucSynchro1(203)` `vtucPilot1(204)` `vtucQuiet2(205)` `vtucPeriodic1(206)` `vtucSynchro2(207)` `vtucChDiscov2(208)` `vtucSynchro3(209)` `vtucTraining1(210)` `vtucSynchro4(211)` `vtucPilot2(212)` `vtucTeq(213)` `vtucEct(214)` `vtucPilot3(215)` `vtucPeriodic2(216)` `vtucTraining2(217)` `vtucSynchro5(218)` `vtucMedley(219)` `vtucSynchro6(220)` `vtucShowtime(221)` `vturG9941(300)` `vturQuiet1(301)` `vturChDiscov1(302)` `vturSynchro1(303)` `vturLineprobe(304)` `vturPeriodic1(305)` `vturSynchro2(306)` `vturChDiscov2(307)` `vturSynchro3(308)` `vturQuiet2(309)` `vturTraining1(310)` `vturSynchro4(311)` `vturTeq(312)` `vturQuiet3(313)` `vturEct(314)` `vturPeriodic2(315)` `vturTraining2(316)` `vturSynchro5(317)` `vturMedley(318)` `vturSynchro6(319)` `vturShowtime(320)`
Xdsl2LdsfResult	Enumeration	`none(1)` `success(2)` `inProgress(3)` `unsupported(4)` `cannotRun(5)` `aborted(6)` `failed(7)` `illegalMode(8)` `adminUp(9)` `tableFull(10)` `noResources(11)`
Xdsl2LineBpsc	Enumeration	`idle(1)` `measure(2)`
Xdsl2LineCeFlag	Bits	`enableCyclicExtension(0)`
Xdsl2LineClassMask	Enumeration	`none(1)` `a998ORb997M1cORc998B(2)` `b997M1xOR998co(3)` `b997M2x(4)` `b998M1x(5)` `b998M2x(6)` `b998AdeM2x(7)` `bHpeM1(8)`
Xdsl2LineLdsf	Enumeration	`inhibit(0)` `force(1)`
Xdsl2LineLimitMask	Bits	`profile8Limit1(0)` `profile8Limit2(1)` `profile8Limit3(2)` `profile8Limit4(3)` `profile8Limit5(4)` `profile8Limit6(5)` `profile8Limit7(6)` `profile8Limit8(7)` `profile8Limit9(8)` `profile8Limit10(9)` `profile8Limit11(10)` `profile8Limit12(11)` `profile8Limit13(12)` `profile8Limit14(13)` `profile8Limit15(14)` `profile8Limit16(15)` `profile12Limit1(16)` `profile12Limit2(17)` `profile12Limit3(18)` `profile12Limit4(19)` `profile12Limit5(20)` `profile12Limit6(21)` `profile12Limit7(22)` `profile12Limit8(23)` `profile12Limit9(24)` `profile12Limit10(25)` `profile12Limit11(26)` `profile12Limit12(27)` `profile12Limit13(28)` `profile12Limit14(29)` `profile12Limit15(30)` `profile12Limit16(31)` `profile17Limit1(32)` `profile17Limit2(33)` `profile17Limit3(34)` `profile17Limit4(35)` `profile17Limit5(36)` `profile17Limit6(37)` `profile17Limit7(38)` `profile17Limit8(39)` `profile17Limit9(40)` `profile17Limit10(41)` `profile17Limit11(42)` `profile17Limit12(43)` `profile17Limit13(44)` `profile17Limit14(45)` `profile17Limit15(46)` `profile17Limit16(47)` `profile30Limit1(48)` `profile30Limit2(49)` `profile30Limit3(50)` `profile30Limit4(51)` `profile30Limit5(52)` `profile30Limit6(53)` `profile30Limit7(54)` `profile30Limit8(55)` `profile30Limit9(56)` `profile30Limit10(57)` `profile30Limit11(58)` `profile30Limit12(59)` `profile30Limit13(60)` `profile30Limit14(61)` `profile30Limit15(62)` `profile30Limit16(63)`
Xdsl2LinePmMode	Bits	`allowTransitionsToIdle(0)` `allowTransitionsToLowPower(1)`
Xdsl2LineProfiles	Bits	`profile8a(0)` `profile8b(1)` `profile8c(2)` `profile8d(3)` `profile12a(4)` `profile12b(5)` `profile17a(6)` `profile30a(7)`
Xdsl2LinePsdMaskSelectUs	Enumeration	`adlu32Eu32(1)` `adlu36Eu36(2)` `adlu40Eu40(3)` `adlu44Eu44(4)` `adlu48Eu48(5)` `adlu52Eu52(6)` `adlu56Eu56(7)` `adlu60Eu60(8)` `adlu64Eu64(9)`
Xdsl2LineReset	Enumeration	`idle(1)` `reset(2)`
Xdsl2LineSnrMode	Enumeration	`virtualNoiseDisabled(1)` `virtualNoiseEnabled(2)`
Xdsl2LineStatus	Bits	`noDefect(0)` `lossOfFraming(1)` `lossOfSignal(2)` `lossOfPower(3)` `initFailure(4)`
Xdsl2LineTxRefVnDs	OctetString	`range: 0..96`
Xdsl2LineTxRefVnUs	OctetString	`range: 0..48`
Xdsl2LineUs0Disable	Bits	`profile8Us0Disable1(0)` `profile8Us0Disable2(1)` `profile8Us0Disable3(2)` `profile8Us0Disable4(3)` `profile8Us0Disable5(4)` `profile8Us0Disable6(5)` `profile8Us0Disable7(6)` `profile8Us0Disable8(7)` `profile8Us0Disable9(8)` `profile8Us0Disable10(9)` `profile8Us0Disable11(10)` `profile8Us0Disable12(11)` `profile8Us0Disable13(12)` `profile8Us0Disable14(13)` `profile8Us0Disable15(14)` `profile8Us0Disable16(15)` `profile12Us0Disable1(16)` `profile12Us0Disable2(17)` `profile12Us0Disable3(18)` `profile12Us0Disable4(19)` `profile12Us0Disable5(20)` `profile12Us0Disable6(21)` `profile12Us0Disable7(22)` `profile12Us0Disable8(23)` `profile12Us0Disable9(24)` `profile12Us0Disable10(25)` `profile12Us0Disable11(26)` `profile12Us0Disable12(27)` `profile12Us0Disable13(28)` `profile12Us0Disable14(29)` `profile12Us0Disable15(30)` `profile12Us0Disable16(31)` `profile17Us0Disable1(32)` `profile17Us0Disable2(33)` `profile17Us0Disable3(34)` `profile17Us0Disable4(35)` `profile17Us0Disable5(36)` `profile17Us0Disable6(37)` `profile17Us0Disable7(38)` `profile17Us0Disable8(39)` `profile17Us0Disable9(40)` `profile17Us0Disable10(41)` `profile17Us0Disable11(42)` `profile17Us0Disable12(43)` `profile17Us0Disable13(44)` `profile17Us0Disable14(45)` `profile17Us0Disable15(46)` `profile17Us0Disable16(47)` `profile30Us0Disable1(48)` `profile30Us0Disable2(49)` `profile30Us0Disable3(50)` `profile30Us0Disable4(51)` `profile30Us0Disable5(52)` `profile30Us0Disable6(53)` `profile30Us0Disable7(54)` `profile30Us0Disable8(55)` `profile30Us0Disable9(56)` `profile30Us0Disable10(57)` `profile30Us0Disable11(58)` `profile30Us0Disable12(59)` `profile30Us0Disable13(60)` `profile30Us0Disable14(61)` `profile30Us0Disable15(62)` `profile30Us0Disable16(63)`
Xdsl2LineUs0Mask	Bits	`eu32(0)` `eu36(1)` `eu40(2)` `eu44(3)` `eu48(4)` `eu52(5)` `eu56(6)` `eu60(7)` `eu64(8)` `eu128(9)` `reserved1(10)` `reserved2(11)` `reserved3(12)` `reserved4(13)` `reserved5(14)` `reserved6(15)` `adlu32(16)` `adlu36(17)` `adlu40(18)` `adlu44(19)` `adlu48(20)` `adlu52(21)` `adlu56(22)` `adlu60(23)` `adlu64(24)` `adlu128(25)` `reserved7(26)` `reserved8(27)` `reserved9(28)` `reserved10(29)` `reserved11(30)` `reserved12(31)`
Xdsl2MaxBer	Enumeration	`eminus3(1)` `eminus5(2)` `eminus7(3)`
Xdsl2MrefPsdDs	OctetString	`range: 0..192`
Xdsl2MrefPsdUs	OctetString	`range: 0..128`
Xdsl2OperationModes	Enumeration	`defMode(1)` `ansit1413(2)` `etsi(3)` `g9921PotsNonOverlapped(4)` `g9921PotsOverlapped(5)` `g9921IsdnNonOverlapped(6)` `g9921isdnOverlapped(7)` `g9921tcmIsdnNonOverlapped(8)` `g9921tcmIsdnOverlapped(9)` `g9922potsNonOverlapped(10)` `g9922potsOverlapped(11)` `g9922tcmIsdnNonOverlapped(12)` `g9922tcmIsdnOverlapped(13)` `g9921tcmIsdnSymmetric(14)` `g9923PotsNonOverlapped(20)` `g9923PotsOverlapped(21)` `g9923IsdnNonOverlapped(22)` `g9923isdnOverlapped(23)` `g9924potsNonOverlapped(26)` `g9924potsOverlapped(27)` `g9923AnnexIAllDigNonOverlapped(30)` `g9923AnnexIAllDigOverlapped(31)` `g9923AnnexJAllDigNonOverlapped(32)` `g9923AnnexJAllDigOverlapped(33)` `g9924AnnexIAllDigNonOverlapped(34)` `g9924AnnexIAllDigOverlapped(35)` `g9923AnnexLMode1NonOverlapped(36)` `g9923AnnexLMode2NonOverlapped(37)` `g9923AnnexLMode3Overlapped(38)` `g9923AnnexLMode4Overlapped(39)` `g9923AnnexMPotsNonOverlapped(40)` `g9923AnnexMPotsOverlapped(41)` `g9925PotsNonOverlapped(42)` `g9925PotsOverlapped(43)` `g9925IsdnNonOverlapped(44)` `g9925isdnOverlapped(45)` `g9925AnnexIAllDigNonOverlapped(48)` `g9925AnnexIAllDigOverlapped(49)` `g9925AnnexJAllDigNonOverlapped(50)` `g9925AnnexJAllDigOverlapped(51)` `g9925AnnexMPotsNonOverlapped(52)` `g9925AnnexMPotsOverlapped(53)` `g9932AnnexA(58)` `g9932AnnexB(59)` `g9932AnnexC(60)`
Xdsl2PowerMngState	Enumeration	`l0(1)` `l1(2)` `l2(3)` `l3(4)`
Xdsl2PsdMaskDs	OctetString	`range: 0..96`
Xdsl2PsdMaskUs	OctetString	`range: 0..48`
Xdsl2RaMode	Enumeration	`manual(1)` `raInit(2)` `dynamicRa(3)`
Xdsl2RfiBands	OctetString	`range: 0..64`
Xdsl2ScMaskDs	OctetString	`range: 0..512`
Xdsl2ScMaskUs	OctetString	`range: 0..512`
Xdsl2SymbolProtection	Enumeration	`noProtection(1)` `halfSymbol(2)` `singleSymbol(3)` `twoSymbols(4)` `threeSymbols(5)` `fourSymbols(6)` `fiveSymbols(7)` `sixSymbols(8)` `sevenSymbols(9)` `eightSymbols(10)` `nineSymbols(11)` `tenSymbols(12)` `elevenSymbols(13)` `twelveSymbols(14)` `thirteeSymbols(15)` `fourteenSymbols(16)` `fifteenSymbols(17)` `sixteenSymbols(18)`
Xdsl2SymbolProtection8	Enumeration	`noProtection(1)` `singleSymbol(2)` `twoSymbols(3)` `threeSymbols(4)` `fourSymbols(5)` `fiveSymbols(6)` `sixSymbols(7)` `sevenSymbols(8)` `eightSymbols(9)` `nineSymbols(10)` `tenSymbols(11)` `elevenSymbols(12)` `twelveSymbols(13)` `thirteeSymbols(14)` `fourteenSymbols(15)` `fifteenSymbols(16)` `sixteenSymbols(17)`
Xdsl2TransmissionModeType	Bits	`ansit1413(0)` `etsi(1)` `g9921PotsNonOverlapped(2)` `g9921PotsOverlapped(3)` `g9921IsdnNonOverlapped(4)` `g9921isdnOverlapped(5)` `g9921tcmIsdnNonOverlapped(6)` `g9921tcmIsdnOverlapped(7)` `g9922potsNonOverlapped(8)` `g9922potsOverlapped(9)` `g9922tcmIsdnNonOverlapped(10)` `g9922tcmIsdnOverlapped(11)` `g9921tcmIsdnSymmetric(12)` `reserved1(13)` `reserved2(14)` `reserved3(15)` `reserved4(16)` `reserved5(17)` `g9923PotsNonOverlapped(18)` `g9923PotsOverlapped(19)` `g9923IsdnNonOverlapped(20)` `g9923isdnOverlapped(21)` `reserved6(22)` `reserved7(23)` `g9924potsNonOverlapped(24)` `g9924potsOverlapped(25)` `reserved8(26)` `reserved9(27)` `g9923AnnexIAllDigNonOverlapped(28)` `g9923AnnexIAllDigOverlapped(29)` `g9923AnnexJAllDigNonOverlapped(30)` `g9923AnnexJAllDigOverlapped(31)` `g9924AnnexIAllDigNonOverlapped(32)` `g9924AnnexIAllDigOverlapped(33)` `g9923AnnexLMode1NonOverlapped(34)` `g9923AnnexLMode2NonOverlapped(35)` `g9923AnnexLMode3Overlapped(36)` `g9923AnnexLMode4Overlapped(37)` `g9923AnnexMPotsNonOverlapped(38)` `g9923AnnexMPotsOverlapped(39)` `g9925PotsNonOverlapped(40)` `g9925PotsOverlapped(41)` `g9925IsdnNonOverlapped(42)` `g9925isdnOverlapped(43)` `reserved10(44)` `reserved11(45)` `g9925AnnexIAllDigNonOverlapped(46)` `g9925AnnexIAllDigOverlapped(47)` `g9925AnnexJAllDigNonOverlapped(48)` `g9925AnnexJAllDigOverlapped(49)` `g9925AnnexMPotsNonOverlapped(50)` `g9925AnnexMPotsOverlapped(51)` `reserved12(52)` `reserved13(53)` `reserved14(54)` `reserved15(55)` `g9932AnnexA(56)` `g9932AnnexB(57)` `g9932AnnexC(58)` `reserved16(59)` `reserved17(60)` `reserved18(61)` `reserved19(62)` `reserved20(63)`
Xdsl2Tssi	OctetString	`range: 0..96`
Xdsl2Unit	Enumeration	`xtuc(1)` `xtur(2)`
Xdsl2UpboKLF	Enumeration	`auto(1)` `override(2)` `disableUpbo(3)`