The MIB module to describe the clock configuration in Processor Switch Module(PXM) in MGX82xx product. Back cards supported for PXM1: PXM-UI : T1 Clock port, E1 Clock Port PXM-UI-S3 : External Clock1 for T1/E1 Clock input. |
cardSpecific | BASIS-MIB |
ciscoWan | CISCOWAN-SMI |
MODULE-COMPLIANCE, OBJECT-GROUP | SNMPv2-CONF |
MODULE-IDENTITY, OBJECT-TYPE, Integer32 | SNMPv2-SMI |
TEXTUAL-CONVENTION | SNMPv2-TC |
Name | Base Type | Values/Constraints |
---|---|---|
Enumeration | rj45Type(1), smbType(2) | |
Enumeration | clkNotPresent(1), clkPresent(2) | |
Enumeration | ohms75(1), ohms100(2), ohms120(3) | |
Enumeration | pxmInbandClock1(1), pxmServiceModuleClock1(2), pxmTopSRMClock(3), pxmExternalClock(4), pxmInbandClock2(5), pxmServiceModuleClock2(6), pxmBottomSRMClock(7), pxmInternalOscillator(8), pxmExternalClock2(9) | |
Enumeration | primary(1), secondary(2), intOscillator(3) |
![]() | .1.3.6.1.4.1.351.110.3.16 | |
![]() | .1.3.6.1.4.1.351.110.3.16.1 | |
![]() | .1.3.6.1.4.1.351.110.3.16.10 | |
![]() | .1.3.6.1.4.1.351.110.3.16.11 | |
![]() | .1.3.6.1.4.1.351.110.3.16.12 | |
![]() | .1.3.6.1.4.1.351.110.3.16.13 | |
![]() | .1.3.6.1.4.1.351.110.3.16.14 | |
![]() | .1.3.6.1.4.1.351.110.3.16.15 | |
![]() | .1.3.6.1.4.1.351.110.3.16.16 | |
![]() | .1.3.6.1.4.1.351.110.3.16.2 | |
![]() | .1.3.6.1.4.1.351.110.3.16.3 | |
![]() | .1.3.6.1.4.1.351.110.3.16.4 | |
![]() | .1.3.6.1.4.1.351.110.3.16.5 | |
![]() | .1.3.6.1.4.1.351.110.3.16.6 | |
![]() | .1.3.6.1.4.1.351.110.3.16.7 | |
![]() | .1.3.6.1.4.1.351.110.3.16.8 | |
![]() | .1.3.6.1.4.1.351.110.3.16.9 | |
![]() | .1.3.6.1.4.1.351.150.72 | |
![]() | .1.3.6.1.4.1.351.150.72.2 | |
![]() | .1.3.6.1.4.1.351.150.72.2.1 | |
![]() | .1.3.6.1.4.1.351.150.72.2.2 |